AI’s demand for faster, more reliable IC testing

Artificial intelligence (AI) models are being applied to almost everything, from helping people write emails to microcontrollers understanding the meaning of IoT sensor data at the edge of the network. This is creating massive demand for AI computing resources, particularly CPUs, GPUs, and xPUs used in data centers to train and run large language models. Even when systems are deployed at the edge of the network, models are generally trained in data centers to accelerate training.

One of the key characteristics of chips used for AI training and inference is their need to ingest and output very large amounts of data at high speed. To avoid connections from causing a bottleneck, today’s AI ICs use very high-speed interfaces operating at up to 64 Gbps per channel, with complex multi-lane configurations to manage the volume of data. In turn, this is challenging IC test equipment makers to rethink how they architect their testers and the components used in critical signal paths to enable robust, efficient testing of high-bandwidth interfaces.

AI test challenge

Modern ICs have several characteristics that make them difficult to test. They often have hundreds, sometimes thousands, of external pins, many of which must be coordinated to set up and run functional tests within the device. They integrate extremely high levels of functionality, which requires more complex test flows. The sophisticated, high-speed interfaces require test systems to be reconfigured when switching to run a loopback test. Any reconfiguration of testing must be automated, as manual intervention or switching test boards will substantially slow the testing process, creating a bottleneck that delays the production of these essential devices.

The low operating voltages of modern ICs also introduce testing challenges. They are more susceptible to electrical noise; it’s much easier to recognize and deal with 100mV of noise injected into a 5V signal than to do the same for 100mV of noise injected into a 1.5V signal. The use of multi-level signaling on high-performance buses at low frequency also means that only a small amount of signal distortion caused by components on the test board can cause testing to fail.

Leading-edge ICs also face testing challenges due to their extremely high clock rates, typically running at several gigahertz. At these speeds, any delay in the signal – even due to long trace lengths – can make testing more difficult. Furthermore, the digital signals at these frequencies behave more like RF signals on a circuit board, requiring components that do not affect the PCB’s transmission line characteristics.

Densely routed high-speed signals, for example, on internal bus structures or between tracks and pins on IC packages, can pick up crosstalk due to mutual coupling between conductors. These reactive elements can undermine the integrity of the signal to the point that its logic state is misread, or cause jitter, i.e., slight delays or advances in the expected arrival time of a signal, which can cause logic errors.

These factors combine to make testing modern GPUs for AI applications a complex task. The test boards must be designed to minimize degradation of high-speed signals while providing switching functionality to automatically reconfigure connections.

Transforming testers

IC test companies build highly performant carrier boards for testing ICs. They allow the device to connect, provide power and control signals, enable the test equipment to capture data, and automatically reconfigure the connections to allow all necessary tests to be performed. This programmable interconnect also optimizes the use of the tester’s various inputs. Boards are developed for each device.

Ideally, the switches used on each test board would be electrically perfect. They wouldn’t attenuate or distort the signals, would take negligible space, consume no power, and switch instantaneously. In the past, it has been possible to compromise as the impact of the switches has not been significant, but the demands of modern high-speed interfaces means that a new switching solution is required.

Traditionally, test systems use electromagnetic (EM) relays to switch signals during testing. These relays do not offer the performance of the ideal switch outlined above. Relays, even the smallest RF devices, are bulky. They also switch slowly because the electromagnetic switch physically moves the contact, introducing delay into the test process. Their mechanical nature means they wear out and become unreliable after many cycles.

Other test switching systems use semiconductor switches. Although they address some of the limitations of EM relays, they have significant ON-resistances that attenuate test signals and non-linear operation that distorts the waveforms of high-speed interfaces.

One bright spot in the development of test systems for high-bandwidth AI ICs is the emergence of a new class of switch, built using microelectromechanical systems (MEMS) techniques derived from mainstream IC processes. Menlo Micro’s Ideal Switch® offers significant benefits for IC testing: it delivers near-zero resistance with a purely ohmic signal path, very high resistance when open, and extremely low switching energy. Its linear operation from DC to tens of gigahertz and fast (sub 10μs) switching make it exceptionally suitable for the high-speed, high-integrity requirements of AI chip testing compared to traditional solutions.

A joint white paper by AI chip leader Nvidia and Menlo Micro describes how these MEMS switches speed up testing of Nvidia’s GPU lineup. The Ideal Switch® is deployed to configure loopback tests for PCIe Gen6 interfaces, PCIe Gen5-based scan testing, and DC measurements, including drive strength and sensitivity. The white paper’s authors say the MEMS switches provide the “low loss, high-linearity performance necessary to ensure reliable loopback validation” needed at PCIe Gen 6 speeds.

Artificial intelligence has the potential to drive innumerable products and services, many of which are yet to be imagined. But they will be, soon. The demand for computing resources everywhere, from data centers to the Edge, will continue to grow exponentially. A key to enabling the fast, efficient production and testing of the ultra-high-performance CPUs, GPUs, and xPUs demanded is Menlo’s switching technology.

 

About the author

Russell (Russ) Garcia is a veteran technology executive with over 30 years of leadership experience in semiconductors, telecommunications, and advanced electronics. As CEO of Menlo Microsystems, he has led the commercialization of disruptive MEMS switch technology across RF, digital, and power systems.

Previously, Russ founded the advisory firm nGeniSys, served as an Executive in Residence at GE Ventures, and held senior leadership roles at Microsemi, Texas Instruments, and Silicon Systems. He also served as CEO of WiSpry and u-Nav Microelectronics, where he oversaw the launch of the industry’s first single-chip GPS device. Russ remains active as a board member and industry advisor.