Did you know that multi-die architectures now represent over 50% of new semiconductor designs, marking a significant shift in chip development strategy? It’s true. There’s now a clear trend towards more multi-die designs, especially in data center, AI, and server applications where the complexity of the chips is too large to fit on a single die.
In the latest EE Training Days webinar on January 16th — now on-demand — we discover why and learn what engineering challenges and solutions benefit from modern multi-die systems, from architecture planning through manufacturing.
In the “A to Z of Multi-Die Design,” technical expert Tim Kogel from Synopsys explores the practical engineering aspects of multi-die design, including thermal management, power delivery networks, and die-to-die interfaces. Through case studies and technical demonstrations, he examines simulation environments that enable architects to validate designs with accuracy levels exceeding 90%. Kogel analyzes how these tools help identify and resolve potential issues during the architecture phase rather than during costly implementation stages.
Do you know how the Universal Chiplet Interconnect Express (UCIe) standard fits into multi-die design and its technical implementation? Kogel examines that, too, and the integration approaches across 2D, 2.5D, and 3D architectures, with detailed analysis of their respective engineering tradeoffs.
This technical presentation includes an in-depth look at simulation and modeling methodologies that have replaced traditional static analysis. Learn about the systems capable of modeling temporal effects and system-level interactions at speeds up to 100,000 cycles per second, with specific examples of how these capabilities translate to practical design improvements.
And watching on-demand doesn’t mean you can’t demand answers to your questions. Go ahead and type what you’ve got in mind into the Q&A widget, and the folks at Synopsys will get back to you. In the meantime, check out these additional resources from Synopsys:
Synopsys Multi-Die Solution (webpage)
Early Architecture Performance and Power Analysis of Multi-Die Designs (whitepaper)
Final Frontier: The Next Generation of 3DIC Interposer/InFO Design (webinar)
Enabling Efficient Multi-Die Design Implementation and IP Integration (whitepaper)
This webinar is a part of EE Training Days 2025 — a series of online educational sessions addressing specific design challenges, new techniques, and engineering skills. Remember to bookmark this page listing the 2025 EE Training Days lineup and register at your convenience.
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