Many semiconductor companies rely on hardware-assisted verification (HAV) to optimize sophisticated monolithic system-on-chip (SoC) designs and chiplet architectures. HAV streamlines verification and validation by integrating emulation, field-programmable gate array (FPGA) prototyping, and virtual platforms. This approach enables design engineers to efficiently verify individual components and system-wide interactions while validating functionality at granular and system-wide levels.
This article discusses the importance of comprehensively optimizing and verifying complex SoCs and chiplet designs to prevent first-silicon failures and costly re-spins. It highlights key application areas for these chips, such as artificial intelligence (AI), machine learning (ML), 5G networks, automotive systems, and edge IoT devices. The article also explores how HAVs efficiently scale to meet the demands of increasingly complex designs. It explains how multi-user support models distribute costs, reducing the total cost of ownership (TCO) over time.
Optimizing power, performance, and area (PPA)
Designing differentiated semiconductor products requires more than replicating hardware specifications on a whiteboard. To accelerate time to market (TTM) and achieve high-yield tape-outs, semiconductor companies must:
- Meet ambitious PPA targets
- Manage complex processing workloads and frameworks
- Validate seamless integration and system interoperability
- Verify the functionality of SoC designs, chiplets, and interconnects
Comprehensive verification of advanced SoCs and chiplets is critical at every stage of design to prevent first-silicon failures and expensive re-spins. Re-spinning a large design at a sub-10-nanometer node can cost over $10 million, while product delays of several months may result in hundreds of millions in lost revenue. Notably, verification now accounts for approximately 50% of a project’s design cycle, driven by increasing complexity from combined hardware and software functionality, higher I/O traffic, and rising power demands.
These complexities demand massive computational resources, requiring billions of cycles to test applications and run performance benchmarks such as MLPerf and AnTuTu (Figure 1). High-performance computing (HPC) chips targeting artificial intelligence (AI) and machine learning (ML) require specialized frameworks and workloads to verify optimal functionality for large language models (LLMs), extensive training datasets, and complex queries.
Chips in advanced driver-assisted systems (ADAS) require verification to ensure rapid inference and real-time decision-making for vehicle control. These systems process petabytes of raw sensor data from LiDAR and machine vision (cameras). Edge AI chips in smart IoT and IIoT devices are validated for low-power, low-latency performance. At the same time, mobile processors in smartphones and tablets must meet consumer demands for performance, power efficiency, and responsiveness.
To achieve optimal PPA, designers co-optimize every chip-related component — from silicon IP to system hardware and software. Functional verification through register transfer level (RTL) regressions, IP performance validation, and compliance checks ensures all components operate as intended in a secure system-level environment. Early-stage performance analysis, power assessments, and test generation are equally critical to ensuring safety, efficiency, and reliability.
Efficiently scaling HAVs for complex designs and advanced nodes
Modern HAV platforms efficiently analyze semiconductor designs ranging from 40 million to over 40 billion logic gates, supporting full system workload execution with complete visibility. Scalable HAV is critical to most verification strategies and design flows, particularly at advanced nodes. These platforms enable in-depth analysis of SoC and chiplet designs across diverse applications, such as AI, ML, 5G, automotive systems, IoT devices, and graphics processing units (GPUs).
By seamlessly integrating hardware emulation, FPGA prototyping, and virtual environments (Figure 2) into a unified workflow, HAV enables efficient management of multi-layered architectures to meet stringent performance requirements and support expanding software functionality.
Comprehensive HAV platforms deliver design visibility, precise analysis, and advanced debug capabilities. They also support power and performance estimation while addressing milestone-specific requirements throughout the verification cycle, including:
- Early-stage verification: use virtual platforms and models, such as software simulators and hardware abstractions, to process software workloads during the architectural phase. Emulators integrate with these platforms to efficiently manage RTL design blocks.
- RTL debugging: as the RTL code stabilizes, perform detailed debugging with full design visibility. Emulators support power analysis and gate-level emulation, ensuring precise analysis of gate-level netlists as the design approaches tape-out.
- Emulation offload: debug efficiently during early verification stages using emulators, then offload stable designs to enterprise FPGA prototyping tools for higher-speed verification. This transition reduces costs and accelerates the process as debugging needs decrease.
- Desktop prototyping: provides a compact, lab-friendly solution for individual users. It enables quick design creation and ultra-fast execution to support rapid iterations.
An integrated HAV strategy ensures efficient, scalable, cost-effective verification and validation workflows, even for the most complex chips and their target software functionality.
Maximizing return on investment (ROI) and reducing TCO
Although hardware emulators remain the most expensive component of HAV platforms, their TCO has significantly decreased due to improved reliability, elimination of dedicated support teams, virtual mode capabilities, and dramatic reductions in per-gate costs.
Evaluated on verification power and flexibility, comprehensive HAV platforms are highly cost-effective. These platforms deliver the performance and capacity required to handle complex debugging tasks involving firmware and hardware-software co-validation. Semiconductor companies further reduce HAV costs over time by adopting multi-user support models, effectively distributing acquisition expenses across multiple teams or projects to maximize resource utilization and lower per-user costs.
Conclusion
HAV streamlines the verification and validation of advanced chip designs, supporting systems with up to 40 billion logic gates by seamlessly integrating emulation, FPGA prototyping, and virtual platforms. This approach helps semiconductor companies meet ambitious PPA targets efficiently, prevent first-silicon failures, and avoid costly re-spins.
