Radiofrequency ICs (RFICs) are found in consumer devices, portable electronics, automotive, military, and medical systems. They typically operate from several hundred MHz to multiple GHz. Those high frequencies present designers with significant layout challenges to ensure proper functioning, including the use of transmission line technology for efficient operation. This FAQ presents several options for RFIC and module floor planning and layout tools.

Designing RFICs requires a broad range of specialized tools like schematic and layout tools, plus simulation software that can handle the complexities of high-frequency operation and transmission line interconnects. In one instance, Ansys and Synopsys have collaborated to provide a comprehensive RFIC design reference flow developed with Samsung Foundry for its 14LPU process technology. The new collaboration is designed to optimize RFIC designs with Ansys’ signoff electromagnetic analysis together with Synopsys’ analog/RF and mixed-signal design and verification solution.

Key elements of the reference flow include the Synopsys Custom Design Family, with the Synopsys PrimeSim circuit simulation solutions, and electromagnetic signoff analysis provided by Ansys RaptorX Electromagnetic Modeling Family, Ansys Exalto Electromagnetic Extraction and Signoff, and Ansys VeloceRF Inductor and Transformer Design Tools.

More automation
Layout is a critical activity since it links RFIC design with manufacturing, but it can be a time-consuming and iterative process. One recent effort to automate layout generation more fully is implemented with a C++-based system that can be used for back-end design and reverse engineering. The goal of the system is to minimize the PPA (power, performance, and area) of the chip while reducing the work required by engineers.

Inputs include a netlist file, PDK information, and optional reference coordinates. The PDK typically includes a component description format (CDF), parameterized cells (PCells), a SPICE simulation model, a physical verification rule file (PVRule), and other components. The PCells are programmable units that allow users to modify parameters and create different PCell instances. The system uses an automated procedure for the layout of RFICs by relying on the device/PCell structure based on the interconnection among circuit topologies.

The system automatically generates an optimized layout using the netlist and PDK information combined with application extension language (AEL) files to customize and extend the capabilities of the design environment. The system streamlines the layout design process and increases design efficiency while minimizing the potential for human error (Figure 1).

From RFICs to RF modules
In addition to using higher frequencies, applications like 5G communications and automotive radar are increasing in complexity, like the use of phased array antennas and replacing analog modulation with digital designs. That often requires the use of modules instead of individual RFICs. Challenges when designing multi-technology modules include:

• Design flows must support the interconnection of devices like RFICs, monolithic microwave ICs (MMICs), phased array antennas, and other components into complex modules using wafer-level packaging, laminates, and other materials. Validation must consider the entire module and include design rule checks (DRCs) and layout versus schematic (LVS) confirmation.
• The use of digital modulation requires new figures of merit like distortion error vector magnitude (EVM). EVM is a comprehensive measure of the transmit quality because it reflects signal defects that affect the magnitude or phase of the transmitted symbol. It captures the sum of imperfections in the device implementation that impact the transmit symbol’s accuracy. It’s expressed in a percentage of RMS or dB.
• Electromagnetic (EM) effects at mmwave frequencies can degrade circuit performance parameters like coupling, losses, and frequency shifts. Those EM effects must be considered as an integral part of the design process including interconnect and packaging design, to ensure that the final design passes verification.
• Transistor gains roll-off at higher frequencies, and overall gain must be increased to take that effect into account. High gains and dense system designs can result in unwanted coupling and amplifier instabilities. To avoid problems, amplifiers need to be analyzed using nonlinear large signal models to ensure proper operation of the final system.

PathWave ADS from Keysight supports a multi-technology design flow for assembling RF ICs, MMICs, packages, and boards into RF modules. It includes a 3D layout for EM-circuit co-simulation and verification, supports amplifier stability analysis, and simulation and optimization of circuits with digitally modulated signals (Figure 2).

Summary
Designing RFICs is getting more complex. Operating frequencies are rising; analog modulation is being replaced with digital modulation, operating environments are proliferating, and multi-technology modules are increasingly common. Fortunately, there’s a range of tools designers can turn to, and more are under development to further improve the efficiency and speed of RFIC and module design efforts.

References
5G Microwave-RF EDA Design Flow, Keysight
From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency
Integrated Circuits, MDPI symmetry
Machine Learning Techniques in Analog/RF Integrated Circuit Design, Synthesis, Layout, and Test,
Elsevier
What is a Radio Frequency Integrated Circuit (RFIC)?, Ansys