Cadence Design Systems announces the Innovus Implementation System for system-on-chip (SoC) development on advanced 16/14/10nm processes and established process nodes. Incorporating the company’s massively parallel architecture with proprietary optimization technologies, Innovus delivers 10 to 20 percent better power, performance and area (PPA) and up to 10x full-flow speedup and capacity gain. The parallel digital implementation incorporates multi-threading and distributed network processing allowing jobs to be distributed across multiple machines on a network and for design blocks of 10 million instances or larger.
“There are two big opposing objectives in SoC design today,” said Rod Metcalfe, Cadence product management group director. “Designers are required to build more chips more quickly and yet are spending too much time on the circuit in order to meet today’s power-performance-area (PPA) demands. Traditional systems have addressed either turnaround time or PPA. Innovus does both.”
Innovus incorporates the company’s GigaPlace solver-based placement technology that is slack-driven and topology-/pin access-/color-aware, enabling optimal pipeline placement, wirelength, utilization and PPA, and providing the best starting point for optimization. According to Metcalfe, GigaPlace considers many different areas of the circuit including time, layer assignment, slot placement and, therefore, arrives at a much better quality placement. Additional features include: advanced timing- and power-driven optimization that is multi-threaded and layer aware, reducing dynamic and leakage power with optimal performance; concurrent clock and datapath optimization that includes automated hybrid H-tree generation, enhancing cross-corner variability and driving maximum performance with reduced power; slack-driven routing with track-aware timing optimization that tackles signal integrity early on and improves post-route correlation; and full-flow multi-objective technology for concurrent electrical and physical optimization to avoid local optima, resulting in the most globally optimal PPA.
The system offers a common user interface (UI) across synthesis, implementation and signoff tools, and data-model and API integration with the Tempus Timing Signoff and Quantus QRC Extraction. Together these systems allow for fast, accurate, 10nm-ready signoff closure. Visualization and reporting tools facilitate enhanced debugging, root-cause analysis and metrics-driven design flow management.
You can find additional Innovus resources including videos, datasheet, white papers, early customer testimonials and more here.
Cadence Design Systems
www.cadence.com
