Modeling and Designing Modern PLL Systems

A Phase Lock Loop (PLL) is a negative feedback control system designed to synchronize an oscillator’s output phase and frequency with a reference signal. PLLs are standard components in applications requiring frequency synthesis, clock recovery, and skew cancellation.

To analyze a PLL effectively, engineers evaluate the system in the complex frequency domain (Laplace transform) and the time domain. This FAQ provides a technical overview of PLL modeling, transient acquisition, and high-performance architecture.

The fundamental mathematical model of a Phase Lock Loop

A Phase Lock Loop is analyzed as a linear system when it is in or near a locked state. The Linear PLL Model, as shown in Figure 1, represents physical components through their equivalent transfer functions:

• Phase detector: This component functions as an error amplifier. It calculates the difference between the reference input phase (ϕ_ref) and the feedback phase (ϕ_fb). The resulting error (ϕ_e) is multiplied by the gain constant K_PD to produce an error voltage (V_e).
• Loop filter: Mathematically represented as F(s), this filter processes the error voltage. It determines the loop’s stability and bandwidth.
• Voltage-controlled oscillator (VCO): The VCO is modeled as a phase integrator with a transfer function of K_VCO/s. This reflects the fact that the output phase is the integral of frequency over time.
• Feedback divider: This block provides a gain of 1/N, where N is the division ratio.

The forward path gain is defined as G(s) = (K_PD*K_VCO*F(s))/s. The closed-loop transfer function is:

H(s) = G(s)/(1 + G(s)/N)

This equation indicates that the PLL functions as a low-pass tracking filter, allowing the output to follow low-frequency phase changes while attenuating high-frequency noise from the reference.

How does the PLL dynamically acquire phase lock over time?

The acquisition of phase lock is a dynamic process characterized by the loop’s transient response. The phase response step response in Figure 2 illustrates how the loop reacts to a reference phase step (e.g., an 8-nanosecond shift).

Most charge-pump PLLs are “Type 2” systems, utilizing two integrators: the VCO and the primary capacitor in the loop filter. The settling behavior is defined by the natural frequency and the damping factor (D):

• Underdamped (D = 0.5): The system is oscillatory. The control voltage fluctuates significantly, leading to VCO overshoot and extended ringing before stabilization.
• Overdamped (D > 1.0): The system does not exhibit ringing but is sluggish. It reaches the locked state slowly, which may be unacceptable for high-speed switching requirements.
• Optimally damped (D = 0.7 to 1.0): Engineers typically design for a damping ratio near 0.707 to balance lock-up speed with minimal overshoot.

Implementing the architecture in high-performance frequency synthesis

Advanced synthesis requirements often necessitate a Fractional-N PLL Architecture (Figure 3) to overcome the constraints of fixed integer division.

In a standard Integer-N PLL, the feedback divider (N) must be a whole number. This requirement couples the reference frequency directly to the channel spacing, often forcing the use of low reference frequencies that limit loop bandwidth and increase phase noise.

The Fractional-N implementation introduces a Fractional Accumulator and a dual-modulus Main Divider (N/N+1). The accumulator toggles the divider between N and N+1 over time. The resulting average division ratio is fractional, allowing for higher reference frequencies and wider loop bandwidths.

A side effect of this dynamic switching is the creation of deterministic phase quantization noise, known as fractional spurs. High-performance designs mitigate this using a Fractional Compensation block and a Compensation Charge-Pump. This circuit injects current into the loop filter to cancel instantaneous phase errors, maintaining low phase noise while benefiting from the faster transient response of a wider bandwidth.

Trade-offs regarding loop bandwidth

Loop bandwidth represents the frequency at which the PLL can no longer track the reference signal. Selecting the bandwidth involves a technical trade-off:

1. Reference noise suppression: A narrower bandwidth is more effective at filtering high-frequency jitter from the reference clock.
2. VCO noise suppression: A wider bandwidth allows the feedback loop to correct the VCO’s intrinsic noise more rapidly.

To maintain performance, designers often use voltage regulators to provide a stable, low-noise power supply to the VCO. This reduces the burden on the loop filter to reject power-supply-induced interference.

Summary

The PLL is a frequency-selective negative feedback system. Its performance depends on the alignment of the linear Laplace model with time-domain requirements for damping and settling. By implementing fractional-N architectures and precise compensation, designers can achieve high-resolution frequency synthesis with optimized noise characteristics.

References

ECEN620: Network Theory Broadband Circuit Design, Texas A&M University
Fractional/Integer-N PLL Basics, Texas Instruments
Phase-Locked Loop Basics (PLL), Dennis Fischette

EEWorld Online related content

What is the math of negative feedback and how is it used to ensure stability?
Phase Locked Loop: A fundamental building block in wireless technology
What is phase noise, and how can I measure it? part 1
What is jitter and what can I do about it (part 1 of 2)?
What is a charge pump and why is it useful? part 1
What is a PLL for analog signals?