Synopsys (has expanded its hardware-assisted verification (HAV) portfolio with new HAPS prototyping and ZeBu emulation systems based on the AMD Versal Premium VP1902 adaptive SoC. The HAPS-200 prototyping and ZeBu-200 emulation systems provide improved runtime performance, compile time, and debug productivity through their EP-Ready Hardware platform, which enables reconfiguration between emulation and prototyping use cases.
The ZeBu Server 5 scales beyond 60 billion gates for SoC and multi-die designs, while HAPS-200 delivers 4X debug performance improvement over HAPS-100. System capacity ranges from single FPGA to multi-rack setups, reaching up to 10.8 BG. The ZeBu-200 extends design capacity to 15.4 BG and achieves 2X runtime performance compared to the previous ZeBu EP2. Debug capabilities have been enhanced with bandwidth increased to 200 GB trace memory per module.
The EP-Ready Hardware platform supports direct and scalable connectivity through cables and hubs, incorporating transactors and speed adaptors for interface protocols. NVIDIA has implemented HAPS-200 in its development process, achieving 50 MHz performance for its software development teams.
Synopsys has expanded its Modular HAV methodology to ZeBu Server 5, focusing on reducing compile time and compute resources for multi-die designs. The company’s Virtualizer tool now includes multi-threading technology, enabling Android boot processes in under 10 minutes. This advancement supports the growing complexity of SoC and multi-die solutions, which are approaching hundreds of billions of gates per chip and hundreds of millions of lines of software code.
The HAPS-200 prototyping system is currently available for general release, while the ZeBu-200 emulation system is being offered to early-access customers. These systems integrate with AMD’s Versal Premium VP1902 adaptive SoC to address verification challenges in AI/ML workloads and multi-die architectures.
