Power-supply supervisors keep circuits in check: part 1

Is my power supply OK? What about my microprocessor? What if something goes wrong? Simulations show what happens if DC voltage drops.

Microprocessors can behave in unwanted ways when their power supplies don’t deliver the expected voltage. Errors can occur, circuits can unexpectedly reset or even go rogue. To prevent such problems, many devices use power-supply supervisory ICs to set things into known states. The following simulations show what can happen and how to prevent them.

Figure 1. This is one of many POR devices available. (Image: Analog Devices)

Many companies, such as Analog Devices, Texas Instruments, ONSemi, NXP, and Diodes Inc., make supervisory devices. Recently, a power supply supervisory IC product announcement from Analog Devices came across my desk. Its purpose was to detect supply voltages that dropped below a certain trip point. Supply voltages that are too low will likely cause the system to perform in unpredictable ways (although probably non-destructively). For example, if the main supply voltage for a microprocessor (µP) drops a bit, the processor may get lost and stop program execution. To fix this problem, a supervisory IC is added that asserts a logic-low Power On Reset (POR) signal that connects to the µP (RESET). See Figure 1. This will halt program execution and restart the program from a known-good state.

But let’s think this through. What if the supply voltage drops a bit more? At what point (as the supply voltage drops) does the supervisory POR IC stop working properly? Does it stop working gracefully? If the POR IC has an open drain that goes low to assert the POR condition, does that output stay low if the POR IC loses its own V_CC? Is it conceivable that the µP could operate at a supply voltage lower than where the POR IC stops functioning? Because if not, then the supervisory IC needs its own power supply, and that supply must always be on. You may wish to consider a power supply with battery backup.

Figure 2. The LTC2934-1 voltage-monitor IC has provisions for detecting two separate voltage levels and producing two separate open-drain control signals. (Image: Analog Devices)

To examine how this might play out, I did an LTSpice simulation of the LTC2934-1. Figure 2 shows a simplified schematic of the function blocks inside the device. It has two comparators and can detect two separate voltage trip points. The lower one generates an inverted Power Fail Output (PFO) control signal, and the upper one generates an inverted Reset (RST) signal after a slight time delay. In the LTC2934-1 version, the outputs are open-drain rather than active pullups, so you need to add your own pullup resistor. The two outputs can be used to force your devices to reset in a controlled fashion.

Figure 3. The LTC2934 controls a system in response to the power supply voltage level. (Image: Analog Devices)

Figure 3 shows the device connected to a generic logic-based system such as a microprocessor.

To simplify my simulation, I used the lower comparator to generate a PFO signal. The RST signal is disabled by connecting the ADJ input directly to V_CC. I added a delay circuit (R3 and C1) to the Power Fail Input, but arranged for V_CC to be on at the start of the simulation. This way I can see what the PFO does under normal operating conditions. The simulated circuit is shown in Figure 4. The Spice simulation presumes that everything starts at t = 0.0 sec. Note that R1 and R2 are made large enough that they impose a negligible load on R3.

Figure 4. In this circuit, the LTC2934-1 is configured as a simple rising voltage detector. (Image: Analog Devices)

Where:

V_C = the capacitor voltage at a specified time after the capacitor starts charging;
V_S = the supply voltage from which the capacitor is charging (10 V in this case);
e = Euler’s constant, a.k.a. the base used in natural logarithms, approximately 2.71828;
t = the time after the circuit is energized that is under consideration (assume the capacitor is discharged, then at t = 0 sec the circuit is turned on);
τ = the RC time constant (100 msec in this case).

If you take the elapsed time to be exactly one time constant, then the exponent to which e is raised is just -1. And if you solve for the percentage of V_S that V_C charges to, you get what is shown in Equations 2a through 2d:

To find out how long it takes (in seconds) for the voltage on C1 to reach a specific value (in volts), we can do some algebraic manipulation of Equation 1 similar to the above steps in Equation 2, as shown in Equations 3a through 3d:

Subtract 1 from each side, multiply both sides by –1, and rearrange:

Then take the natural log of each side, swap the left and right sides, and we get:

We want to find out the time t, so we multiply each side by the time constant τ, and we get:

For the voltage on C1 or the top of R2 to get to 0.42 V, we can substitute our known values in Equation 3d as shown in Equations 4a through 4d:

I simulated the circuit from Figure 4 and got the results shown in Figure 5. I marked the waveform for PFO with blue arrows because it’s not particularly obvious at first glance, and the red arrow shows the rising voltage on C1. This simulation pretty closely matches my calculated values, giving me confidence in my simulation’s ability to accurately represent reality.

Figure 5. The LTC2934-1 simulation shows the PFO node snaps HI around 4.8 ms as expected.

Now, what happens if V_CC for the LTC2934 rises at the same time as the voltage we want to monitor? In other words, if I change the circuit to look like Figure 6 so that the supply and the monitored voltage rise in unison, what happens?