Power-supply supervisors keep circuits in check: part 2

Is my power supply OK, and what if it isn’t? Is my microprocessor still working?

In part 1, we examined the operation of power supply supervisory ICs that can detect when the supply voltage is too low, and what might happen if so. We will continue that analysis and then consider ways to keep an eye on the microprocessor to make sure it’s still alive.

Power supervisory circuit — Figure 1. The LTC2934-1 is configured as a simple rising voltage detector.

Here’s the circuit we used at the end of part 1, repeated as Figure 1. Note, again, all the resistor values except R3 are significantly larger than R3, so that the amount of loading on the R3-C1 network is negligible. The voltage being monitored and the IC’s supply voltage rise in tandem.

Figure 2. The LTC2934-1 simulation shows the PFO node performing oddly.

Look at the simulation results shown in Figure 2. I ran the simulation out to just 50 ms (by changing the second term in the .tran statement) so I could get a close look at the operation in that time span.

Figure 2 shows the +V_CC supply voltage (in blue with red arrow) rising exponentially as we’d expect, but it shows PFO node performing oddly. As the supply voltage rises from zero, PFO rises with it via the R4 pullup resistor (the ‘2934 PFO FET is off). At about 7 ms to 8 ms after the power turns on, the internal circuitry has sufficient voltage and comes alive; PFO switches LO. Finally, when +V_CC is high enough to make the PFI node high enough, PFO is released (goes HI).

This operation raises an important issue. At +V_CC up to about 0.7 V, PFO is not asserted. In this particular configuration, above +V_CC of 1.6V, PFO is not asserted – but that’s because I picked an R1 and R2 rather arbitrarily just to get a functioning circuit. The 0.7 V level is the trouble spot. Most other circuitry in the system will likely not function with a supply voltage of 0.7 V — but what if it does?

To make the circuit more like what we’d have for a real-world system operating with a 10 VDC bus, let’s change the trip point of the voltage monitor circuit to 9.5 V. Recall that the PFI voltage trip point is 0.4 V. We’ll leave R1 at 100k and calculate R2 using the voltage divider formula as shown in Equation 1a:

Where:

V_OUT = the output voltage from the junction of the top and bottom resistors (0.4 V);
V_IN = the supply voltage feeding the top resistor (9.5 V);
R_BOT = the resistance of the bottom resistor (100 k);
R_TOP = the resistance of the top resistor.

Plugging the values and making all resistor values in kilohms, we get Equation 1b:

Divide each side by 9.5 to get Equation 1c:

Reducing the left side fraction and multiplying both sides by [R_TOP+100], we get Equation 1d:

Multiply out the left side of the equation, and we get Equation 1e:

Rearranging and combining like terms, we get Equation 1f:

And finally, dividing both sides by 42.1×10^-3gives us Equation 1g:

Power supply supervisor — Figure 3. This version detects a supply voltage higher than my previous version — in this case, 9.5 V.

We’ll use the nearest standard 5% value of 2.2 M*Omega; as shown in Figure 3.

The results of the simulation are shown in Figure 4a. From V_IN of 0.0 V to about 0.7 V, the performance is again troublesome. Figure 4b provides a close-up view of what happens right after power-up.

Power supply circuit — Figure 4. The 2934 performance looks better (a), but there may still be a problem. In (b), I again zoomed in by changing the schematic .tran statement’s second term to 50 msec.

The PFO looks more like what we would expect from a voltage monitor for a +10 VDC supply, except for that pesky glitch when the supply output is around 0.7 V.

To make sure this isn’t an anomaly, I reworked the circuit to function as a monitor for a 3.3 VDC supply. I set the low voltage trip point at 3.1 V. The circuit is shown in Figure 5. You can use a 665 kΩ or 681 kΩ, 1% resistor for R2.

The simulation results are shown in Figure 6. Once again, from +V_IN of 0.0 V to about 0.7 V, the performance is troublesome.

As I mentioned above, most other circuitry in the system will likely not function with a supply voltage of 0.7 V, but it is possible that some circuits might.

Figure 5. This is a 3.3 V monitor that asserts a PFO below 3.1 V. Sort of.

As a design engineer of such circuits, it’s your responsibility to make sure your design operates properly. You may need to add additional components to force PFO to stay low until +V_CC is for certain high enough. Or, to go back to where we started, you will probably want to make +V_CC to the supervisory IC always on.

For a more detailed look at the problems you might encounter, you can perform a Failure Mode and Effects Analysis and consider what happens with single-point failures.

Power supply circuit problem — Figure 6. This plot clearly shows the PFO problem, where it fails to rise with the power supply voltage.

Can one failure cause serious problems? If one failure occurs and it is invisible — if the system keeps operating normally — does a second failure cause serious problems? Doing this analysis will bring to light possible severe problems: Do the failure modes create unsafe conditions? Will the equipment be damaged? Will users of the equipment be hurt?

Now that we’ve opened up this can of worms and discovered we can’t get the worms back in the can, let’s consider whether we need to monitor our power supply rails for an over-voltage condition. Here’s a hint: We do. The simpler devices don’t monitor for overvoltage. If the supply voltage exceeds the maximum operating voltage per the devices’ data sheets, they will be adversely affected. Overheating or destructive damage to system components downstream from the supply (so, pretty much everything else) is probable. How they perform in a damaged state is anybody’s guess, but the same questions and considerations cited above apply.

Figure 7. This is a typical voltage supervisor (similar to the previous devices we looked at) + WDT IC showing the internal structure in (a) and the typical usage in (b). Image: Diodes, Inc.

There are more complex supervisory devices that combine the power supply monitoring with a device called a Watchdog Timer (WDT). A WDT typically monitors one output of a µP. The code running on the µP is written to not only execute its regular functions but also toggle its WDT output HI and LO at regular intervals. This action will reset a timer in the WDT IC so it never times out. If the WDT input to the WDT IC ever gets stuck (at either HI or LO), the timer times out and forces a RESET to the µP. See Figure 7.

The WDT and voltage monitor will provide a large measure of reliability to your µP system, especially once you think through the various failure modes you may encounter. For a more detailed analysis, you can simulate your µP plus WDT circuitry in Spice (assuming the version you use has a model created for the devices you’re using). N.b.: Make sure the models you’re using have been designed to accurately simulate device operation down to power supply levels in the tens to hundreds of millivolts.