Power ICs cover a variety of functions, from high voltage application-specific ICs (HV-ASICs) to power management ICs (PMICs). Each type of power IC has unique design challenges and needs specific design tools. This FAQ reviews some of the challenges related to HV-ASICs for applications like gate drivers for power semiconductor devices, pin drivers for automatic […]
Cadence
Electrical noise, Part 1: Introductory concepts
Electrical noise is a consideration that engineers think, talk, worry, sometimes obsess about, and deal with nearly all the time, with few exceptions. In many applications, it is the limiting factor on ultimate achievable system performance. If it were not for the existence of noise, many design situations would be far, far easier. Noise is […]
Top analog threads on EDAboard.com – September
(editor’s note: Intrigued by the problem? Have a question or another solution? Then click the “Read more” link and follow the conversation on EDAboard.com or log in to EDAboard and participate in the analog forum threads.) How do I design this darn differential amplifier? I’ve been trying to design a differential amplifier with the following […]
Top analog threads on EDAboard.com – August
(editor’s note: Intrigued by the problem? Have a question or another solution? Then click the “Read more” link and follow the conversation on EDAboard.com or log in to EDAboard and participate in the analog forum threads.) MOSFET getting very hot – In this schematic, the VCC feed with a less than 1 A MOSFET gets […]
Design software facilitates chip/package/board development efforts
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence® Virtuoso® System Design Platform, a formal, streamlined and automated co-design and verification flow between the Cadence Virtuoso platform and Allegro® and Sigrity™ technologies. This higher level of integration enables engineers to design concurrently across the chip, package and board. By automating what has until now been a manual process, the Virtuoso […]
Top analog threads on EDAboard.com – February
(editor’s note: Intrigued by the problem? Have a question or another solution? Then click the “Read more” link and follow the conversation on EDAboard.com or log in to EDAboard and participate in the analog IC forum threads.) Making gain positive and NF less than 7.0 dB – I have designed a mm-wave amplifier, as I intend to […]
How IoT and mixed-signal designs will drive SiP tech in 2016
By Ian Dennison As the Internet of Things (IoT) becomes an increasingly competitive market, we should, in 2016, expect new package and board technologies to provide much of the innovation needed for successful IoT products. Since IoT products are driven by the need for the smallest form factor (think wearables) and ultra-low power (for longer […]
Low-power sensor fusion platform seamlessly integrates into wearables
Cadence Design Systems, Inc. (NASDAQ: CDNS) and CyweeMotion Ltd., today announced that CyweeMotion’s Sensor Fusion Hub™ software has been optimized for Cadence Tensilica Fusion digital signal processors (DSPs). This solution delivers a fully optimized, low-power sensor fusion platform for seamless integration into mobile or wearable devices. The Sensor Fusion Hub technology from CyweeMotion is sensor […]
Techniques to speed up SoC RTL and physical synthesis
David Stratman and Vinay Patwardhan, Cadence In the more complex world of today’s SoCs, you’re integrating a large number of third-party IP blocks with your own highly tuned RTL, while aggressively pushing frequency in the face of lower power requirements and area budgets. You also want to ensure a reliable handoff to place and route […]
