Texas Instruments (TI) (NASDAQ: TXN) introduced a new family of clock generators that provides ultra-low jitter of 100 femtoseconds (fs) and flexible, unique pin control options. Compared to conventional reference clock solutions, the new clock generators’ jitter performance enables system designers to optimize system timing margins and bit error rate (BER) to reduce data transmission errors. This allows for more reliable communications, networking, server, computing, and high-performance industrial equipment. LMK033x8 clock generators also offer versatile features to reduce design cycle time by facilitating easy prototype design and evaluation. For more information, see www.ti.com/lmk033xx-pr.
Key features and benefits of LMK033x8 clock generators
Ultra-low jitter performance enables flexible jitter budgeting: Up to two high-performance PLLatinum™ fractional-N phase-locked loops (PLLs) with eight outputs enable ultra-low jitter performance of 100 fs root mean square (RMS) over multiple integration bandwidths (1 KHz-5 MHz and 12 KHz-20 MHz). Designers can take advantage of the ultra-low jitter to improve their system BER and increase the reliability of their telecommunications infrastructure equipment.
Flexible, simple configuration: A unique pin-mode control feature enables designers to easily select from 71 pre-programmed frequency startup plans compared to one-time programmable memory offered by competitors. Integrated electrically erasable programmable read-only memory (EEPROM) enables easy customization, while the I2C interface gives system designers complete control of device configuration.
Reduced design cycle time: Glitchless fine/coarse frequency margining enables designers to simplify the stress and compliance testing of their systems during design verification and process verification (DVT/PVT) of prototypes.
Immune to supply noise: Integrated low-dropout regulators (LDOs) provide immunity to power-supply noise without requiring complex filter designs.
Tools and support to speed design
Evaluation modules (EVMs) enable designers to quickly and easily evaluate the devices. The LMK03328EVM is available today, and the LMK03318EVM will be available in 4Q 2015 from the TI store and authorized distributors for US$299.
TI’s WEBENCH® Clock Architect tool simplifies the design process for the LMK033x8 family, as well as for other TI clock and timing devices. The tool can recommend a single- or multiple-device clock-tree solution from a broad database of devices to meet system requirements. It features PLL filter design, phase-noise simulation, and the ability for designers to optimize clock-tree designs for their performance and cost requirements.
Support is available in the TI E2E™ Community Clock and Timing forum, where engineers can search for solutions, get help, share knowledge, and solve problems with fellow engineers and TI experts.
Package, availability and pricing
LMK033x8 clock generators come in a 7-mm-by-7-mm quad-flat no-lead (QFN) package. The LMK03328 dual-PLL eight-output clock generator is available today and priced at US$10.00 in 1,000-unit quantities (1ku). The LMK03318 single-PLL eight-output clock generator will be available in 4Q 2015 and will be priced at $7.50 in 1ku.
These clock generators are the newest members of TI’s clock and timing portfolio, including LMK03806 and CDCM6208 clock generators, which also offer high performance and flexibility. TI offers a broad timing portfolio that also includes ultra-low-additive jitter fan-out buffers like the LMK00301 universal differential buffer and the LMK00338 PCI Express Gen-3-compliant high-speed current steering logic (HCSL) buffer, which complement the LMK03328 and LMK03318.
TI
www.ti.com
