Understanding ADC specs and architectures: part 1

Analog-to-digital converters are the heart of most test equipment, setting the stage for the digital processing of analog signals.

Several posts over the past year or so have involved digital signal processing. For example, we have covered the fast Fourier transform (FFT), the inverse FFT, and discrete convolution. To perform these operations on real-world signals, we must digitize them, and the device that does that is the analog-to-digital converter (ADC).

Do ADCs have applications outside of test and measurement?

Yes indeed. ADCs are key components in digital oscilloscopes, spectrum analyzers, vector network analyzers, and other high-performance digital instruments. Still, while the test-and-measurement industry is a demanding customer for ADCs, the research firm Market Research Future cites consumer, automotive, industrial, and medical applications as key segments, with the Internet of Things and the emergence of artificial intelligence (AI) as key drivers. You probably have many ADCs in your car and personal electronics. The firm forecasts that the ADC market will grow from $17.18 billion in 2025 to $31.23 billion by 2034 for a CAGR of 6.86%.

What would be an application for an ADC involving AI?

Predictive maintenance in an industrial facility would be one. For example, you could use sensors to monitor the vibration, acoustic, and temperature data of a motor bearing. ADCs could digitize that data and send it to a real-time microcontroller unit (MCU) equipped with neural-network processing capabilities. That MCU could analyze data patterns and predict time to failure, allowing for orderly shutdown and repair.

How do ADCs work, and what are their key specifications?

The key specifications are resolution and bandwidth — how accurately and quickly can the ADC resolve an analog input signal? An ideal ADC would have infinite resolution and bandwidth, but obviously, that isn’t possible.

Let’s start with the resolution. Figure 1 at the top shows a three-bit ADC. That’s not a common type — most converters range from eight to sixteen or more bits – but the three-bit version is useful for demonstrating the concept. The device converts an analog input voltage V_IN to a three-bit digital code represented by D₀ to D_2, ranging from binary 000 to 111, where the rightmost digit is the least significant digit (LSB). The leftmost digit is the most significant digit (MSB).

Figure 1. ADCs can present their outputs in parallel (top) or in series (bottom).

What about the bottom device?

Note that the top device presents its output in parallel, using three pins. The bottom device, in contrast, sends its output to an MCU or other device serially (with the LSB first for the implementation shown here), most likely using a standard interface such as SPI, I²C, I3C, PCIe, or USB.

What else do we need to know about resolution?

Figure 2. A three-bit ADC has eight quantization levels.

For our three-bit device, we have eight possible quantization levels. In general, an n-bit converter will have 2ⁿ quantization levels. For a given full-scale (FS) input voltage V_FS, the converter can theoretically resolve a voltage of V_FS/n, the analog equivalent of the LSB, so for a 1 V FS input, our three-bit ADC can theoretically resolve 1 V/8 = 0.125 V, which corresponds to the LSB. The actual voltage, however, depends on the coding scheme that a particular converter uses. Figure 2, for example, uses a version of a coding scheme called Unipolar Straight Binary coding in which any input value less than one-half LSB, or 0.0625 V (a span of 0.0625 V) will be coded as 000. In comparison, a value between 0.0625 V and 0.1875 V (a span of 0.125 V, or 1 LSB) will be coded as 001.

What should I know about ADC specifications?

As noted previously, the ideal ADC doesn’t exist. Figure 2 shows the performance of an ideal three-bit ADC, and even that doesn’t exist. Specifications such as differential nonlinearity, integral nonlinearity, offset error, and gain error describe how an actual ADC differs from an ideal ADC for a given resolution. We’ll take a closer look next time. Then, we will look at bandwidth and how it’s affected by various ADC architectures, including the flash, pipeline, successive-approximation-register, and sigma-delta architectures.