Understanding ADC specs and architectures: part 2

Specifications such as gain error, offset error, and differential nonlinearity help define an analog-to-digital converter’s performance.

Figure 1. An ADC will have a maximum quantization error EQ(MAX) and can also exhibit positive (red) or negative (yellow) offsets with respect to its ideal response (blue).

In part 1 of this series, we discussed an ideal analog-to-digital converter (ADC), noting that it would have infinite resolution and bandwidth. Then we looked at the real world of practical inverters and how their resolution, expressed in a finite number of bits, introduces quantization error. We concluded with a figure containing a response that looks like the blue stair steps in Figure 1.

We can put a number to the maximum quantization error, which we will call E_Q(MAX). The straight light-blue line in the figure represents the ideal response with no quantization error. The quantization error reaches its maximum immediately following or preceding a transition and is calculated as follows:

Where V_FS is the full-scale (FS) voltage and n is the ADC resolution in bits. For our three-bit ADC with an FS input voltage of 1 V, E_Q is 62.5 mV, or 6.25% of V_FS, or one half of a least significant bit (LSB).

Q: What are the red and yellow traces?
A: While the blue trace represents the “ideal” behavior of a three-bit ADC, the device can exhibit other errors besides the quantization error. These additional errors include positive and negative offset errors, which we can express in terms of least significant bits or percent of full-scale (FS) voltage. In Figure 1, the red trace represents an offset error of 1.25 LSBs, and the yellow trace represents an offset error of -1.25 LSB.

Q: What are some other potential sources of error?
A: Gain error is another, as illustrated in Figure 2. As shown by the blue trace, the converter should transition from 010 to 011 at five-sixteenths of the FS analog input voltage. Still, the red trace shows an earlier transition at one-fourth of the FS analog input, indicating that the gain is too high. The error regarding LSBs at the full-scale input can be expressed numerically. In the figure, the gain error for the red trace is 1.5 LSBs, and for the yellow trace, -1.5 LSBs.

ADC — Figure 2. Compared to the ideal response (blue), gain error can be positive (red) or negative (yellow).

Q: What can we do about these errors?
A: The good news is that we can compensate for offset and gain errors. There are other errors, however, for which we cannot compensate, such as differential nonlinearity (DNL). Figure 3 shows the basics. Note that the red non-ideal staircase corresponds to the ideal response for the first (000 to 001) and last (110 to 111) transitions, most likely because we have compensated for gain and offset errors. Elsewhere, each step should have a width of 1 LSB. There are, however, obvious differences that we can quantify using DNL. You calculate DNL for each code except the first and last by subtracting the ideal step width from the actual step width. For example, you can calculate the DNL for code 001, which has a 1.25-LSB width, as follows:

Similarly,

Figure 3 lists the code step widths in red and the corresponding DNLs in blue.

ADC — Figure 3. You can derive the DNL (blue text) from the step width (red text).

Q: Wait, I notice that code 011 doesn’t have a step — what’s up with that?
A: Right, no analog input level will produce the output code 011, and the device is said to have a missing-code error. Because the step width for 011 is zero, we calculate the DNL as follows:

Q: What’s the bottom line on DNL?
A: Total DNL is often specified as the lowest to highest DNL over the device’s range. For our example, the worst-case DNL is -1 LSB to +0.5 LSB.

Q: What else should I know about ADC specifications?
A: We’ve looked at some DC specifications: offset, gain errors, and DNL. Another related DC specification is integral nonlinearity (INL), which examines the cumulative effect of DNL. We will take a closer look in part 3, and then we will examine sampling rate, throughput, AC specifications, and different ADC architectures.