Understanding ADC specs and architectures: part 3

Integral nonlinearity tracks the cumulative effects of an ADC’s differential nonlinearity.

In part 2 of this series, we discussed several sources of error in an analog-to-digital converter (ADC), including gain, offset, missing-code error, and differential nonlinearity (DNL). We concluded with an illustration of a waveform with varying levels of DNL superimposed on the staircase representing the “ideal” response of a three-bit ADC.

Figure 1. A three-bit ADC has an ideal step width of 1 LSB and a maximum quantization error of 0.5 LSB.

Q: Last time, you mentioned integral nonlinearity (INL). How does that compare with DNL?
A: Let’s step back and reconsider the “ideal” response of a three-bit ADC, the solid staircase in Figure 1, vs. the ideal response of an ADC with infinite resolution, the dashed line. Note that, except for the 000 and 111 codes (which vary in accordance with the coding scheme described in part 1), the step width is 1 LSB, and the maximum quantization error is 0.5 LSB.

As an aside, carpenters would call what we’re calling the step width a “going,” or the step dimension from the top of one riser to the bottom of the next; width is the staircase dimension perpendicular to the direction of travel. But in the cross sections we are looking at, the dimension appears to be a width, which is the term commonly used in the literature on data converters, and we’ll continue using it here. Otherwise, keeping with our staircase analogy, we take delivery of some treads and note that one half has a width of 0.5 LSB and the other half 1.5 LSB, giving them DNLs of -0.5 LSB and 0.5 LSB, respectively.

Figure 2. This alternating red and blue tread arrangement results in a worst-case deviation of 1 LSB.

We do the best we can with what we have received and build the staircase in Figure 2, where the red steps have a width of 0.5 LSB and the blue steps have a width of 1.5 LSB. Like DNL, each step has its own INL, and we characterize an ADC by the worst-case INL. In Figure 2, the worst-case performance occurs at the beginning of each blue step, where the deviation from the ideal response is 1 LSB.

Q: I notice that the red and blue steps alternate. Does that affect INL?
A: Yes. In Figure 3, we have rebuilt our stairway with all the red treads toward the bottom. We can see that as we climb up, the nonlinearity error accumulates, and we reach a worst-case deviation of 2 LSBs from the ideal at step 100.

Q: So, the INL of the device is 2 LSBs?
A: No. Manufacturers have at least a couple of ways of specifying INL. One is based on the position of the actual rising edges relative to the position of the ideal rising edge [1], and another is based on the distance from the midpoint of an actual step to the midpoint of the ideal step [2]. Figure 3 shows this latter version, for which the INL is 1.25 LSB.

Figure 3. Putting the narrower red treads at the bottom of the staircase results in a worst-case error of 2 LSBs and a maximum INL of 1.25 LSB.

Q: What’s the bottom line on these DC error effects we have been studying?
A: First, we can see that the DNL spec is not definitive. Worst-case performance depends on how DNL errors are distributed throughout the ADC’s transfer function, which INL indicates. Ultimately, you will want to know the total accuracy error, also called total unadjusted error, which is heavily dependent on your application and generally does not appear on a data sheet. Total accuracy error is influenced by gain and offset error and INL, but you can’t simply sum those errors to get a meaningful value [3] because they are uncorrelated with specific input voltages. Experimentation and measurement are your best options, and one recommendation, if you can sacrifice some dynamic range, is to avoid operating near either end of the transfer function [4].

Q: What about the AC specifications?
A: The AC or dynamic specs range from the obvious, such as sample rate, to the more esoteric, such as the effective number of bits (ENOB). We will take a closer look in part 4.