Siemens Digital Industries Software has released the Innexis product suite to complement its Veloce hardware-assisted verification and validation system.
The Innexis suite addresses software development needs in early IC development phases through three core products. The suite enables hardware/software development flow from virtual to hybrid to full RTL, provides an architecture native virtual platform, and includes a simulation backplane for digital twins in PAVE360 software.
The suite supports shift-left software development and IP verification processes for complex chip designs with demanding software workloads. This approach helps identify issues earlier in the development cycle.
The Innexis Developer Pro software creates a connected development flow environment for SoC design, supporting hardware-software co-development and validation. It enables modeling of SoCs with heterogeneous cores and custom SystemC model components, offering both virtual plus RTL hybrid mode and full RTL emulation capabilities.
The Architecture Native Acceleration (ANA) software operates as a cloud-based virtual platform on Arm-based servers, providing higher execution speeds compared to instruction set simulation platforms. It can run on local Arm-based servers and offers browser-based access and tools.
The Virtual System Interconnect software connects multi-behavioral virtual and physical subsystems for system-level digital twin platforms, supporting various communication protocols. It integrates with Developer Pro and ANA SoC models for system-level software development and RTL verification.
