The ABCs of functional verification techniques

By Aijaz Fatima of  Siemens business

Functional verification is the process of demonstrating the functional correctness of a design with respect to the design specifications. Functional verification does not confirm the correctness of the design specification and assumes that the design specification is correct. It is one of the most challenging steps of the IC design cycle, and is the main reason for IC re-spin.

Purpose

• Functional correctness of individual IPs
• Internal module communication
• External module communication
• End to end functional paths
• Pad connectivity
• Clock and reset circuits
• Power up and down sequence
• Complete integration of all IPs

 

Functional Verification Techniques

Static Verification

Static verification is the process of verifying the design against some predefined rules without executing the design. It allows you to verify your design at an early stage, without any stimulus or setup, and hence is performed early in the IC design cycle, that is, as soon as the RTL code is available. It does not perform any timing checks. The sooner a bug is found, the easier it is to fix it.

Purpose

The purpose of static verification is to reduce the verification effort at the RTL level.

Static Verification Techniques

Advantages

• Detects bug early in the design cycle
• Less time consuming
• Reliable
• Faster
• Exhaustive
• Large designs are easily handled

Mentor, A Siemens Business, offers a broad spectrum of static and formal solutions and applications, including Questa® Formal Verification, Questa Clock-Domain Crossing (CDC), Questa Reset Domain Crossing (RDC), and the Questa Formal Verification Apps. These formal-based technologies complement simulation in a number of key areas.

Functional Simulation

Functional simulation is the process of verifying the functional behavior of a design by simulating it in software. It does not consider the timing delays of the internal logic or interconnects, and is not helpful in software development.

Purpose

The purpose of simulation is to verify the individual IPs or the individual blocks of the IC. System-level verification is not possible with functional simulation.

Simulation Setup

Workflow

 

Advantages

• Quick to set up
• High visibility in the design
• Bugs are identified early in the design
• All corner cases of the designs are verified
• Not expensive

Limitations

• Very slow speed
• Complex designs are not easily simulated
• Verification of the entire IC is difficult
• All possible scenarios and states are not covered
• Verification of software is not possible
• Timing-related issues are not identified

The Questa advanced simulator from Mentor, A Siemens Business is a leader in this space. It combines high-performance and high-capacity simulation with unified advanced debug and functional coverage capabilities along with the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF, and UVM.

FPGA Prototyping

FPGA prototyping is the process of verifying the functionality of the system (IC) on FPGAs.  With the rise in the complexity of ICs and the increasing demand to shorten the time to market of ICs, FPGA prototyping remains a key solution.

Purpose

The purpose of FPGA prototyping is to verify that the design operates as expected when it is driven with live data, and all its external interfaces are working correctly.

Workflow

Advantages

• High speed
• Early software development and validation
• Useful for verifying critical IPs used in applications like aerospace, military, medical etc.
• Complete IC design is verified
• Reduces risk of re-spin of ICs
• Reduces time to market

Limitations

• Slow to compile (than emulators)
• Partitioning of designs is error-prone and tedious
• ASIC to FPGA clock conversion is complex
• FPGA to FPGA interconnections are limited
• Very limited debug capability
• Long bring up time as ASIC code has to be converted to FPGA code
• Expensive and time consuming to build the FPGA board

Emulation

Emulation, also called as pre-silicon validation, is the process of verifying the functionality of the system on a hardware device called as an emulator. An emulator can handle both system-level designs (in C, C++, or SystemC) and RTL designs (in Verilog or VHDL). Emulators are much faster than simulators. A design that takes days in simulation, will take only hours in emulation.

Purpose

The purpose of emulation is to find issues in the system level design with live data, to verify the system integration, and for development of the embedded software.

Workflow

The emulator workflow is similar to the FPGA prototyping flow, except that you use emulator tools in place of the FPGA prototyping tools.

Advantages

• Higher speed (than simulators)
• Higher design visibility (than FPGA prototyping) and hence higher debug capability
• Faster to compile (than emulators)
• Parallel verification of many designs possible
• Just like simulators, emulators can be stopped and later started from the same point
• Verification of embedded software is possible

Limitations

• Slower to compile (than simulators)
• Very expensive
• Long set up time
• Not all functional paths are covered

Mentor’s Veloce Strato emulation platform is the leading high-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs.

Universal Verification Methodology (UVM)

UVM is a set of coding guidelines that has a well-defined testbench structure. It is written in SystemVerilog and provides a SystemVerilog base class library (BCL) for building advanced reusable verification component. It was developed by the Accellera Systems Initiative, an EDA standards body, with significant guidance and input from Mentor.

Purpose

IPs are highly complex and it takes time to verify them completely. The standard test benches are not reusable and the verification engineers have to create the test benches from scratch. Due to tight schedule pressures, a verification methodology is highly advisable. UVM has a fixed testbench architecture that makes the testbench highly reusable and saves considerable amount of time.

UVM Architecture

The UVM architecture has the following components:

• Configuration Object – Configures the environment, agent, and test
• Sequencer – Sends sequences to driver
• Driver – Converts sequences to pin wiggles
• Interface – Helps the testbench to communicate with the DUT
• Monitor – Detects transitions on the interface
• Coverage – Collects coverage information from Monitor

Advantages

• Reduces coding effort, and enables high level of reuse
• Supports constrained random verification methodology
• Extensive stimulus generation
• Decreases verification cycle
• Supported by major simulators and emulators

Limitations

• Practically none, except that UVM is a vast topic and needs considerable technical expertise.

Summary

Functional verification is a very important aspect in the IC design cycle. It is imperative that the design is functionally verified and any potential bug is eliminated at an early stage. With the advancement in the design techniques, verification engineers should also adopt the latest verification methodologies.

To improve the productivity and performance of the designs, EDA vendors such as Mentor, a Siemens business, continuously improve their tools and provide new verification methodologies. Mentor’s Questa Verification Solution is a complete verification platform, and its emulator Veloce is one of the best emulators present in the market.