What Will 2015 Bring? A New Electronics System Design Imperative

By Chi-Ping Hsu

A new year approaches and with it comes fresh new challenges for design engineering teams and for us as key ecosystem partners. The biggest challenge that we face as an industry is one that has begun to form in recent years and will fully flower in the coming year:

• How do we enable more complex electronics systems, as we dive deeper into advanced nodes and attempt to satisfy increasingly insatiable customer demand for more and more functional technology?

Let’s look at some of the crucial elements of system design enablement that will take hold in the coming months.

Shift Left

The simultaneous, related drives for faster time to market, differentiation, and profit drive big changes in the way that electronics products will be designed in 2015 and beyond. These changes are underway and have been captured under the umbrella moniker of “shift left.”

Shift left’s essence is the need to understand how any and all dependencies in the product planning and development process can be made to overlap in time.

For example, early software development helps enable software-driven verification methodologies that can be used to verify that the integration of subsystems does not break the design, and performance and energy can be optimized in the system context with both hardware and software optimizations possible.

Numerous design processes are shifting left, but let’s take just one as an another example: The added difficulty associated with high-performance mixed signal IP, such as DDR4 PHY in 16nm/14nm FinFET technologies, needs to be proven early in the process decision lifecycle.  For this reason, foundries, EDA companies and IP providers collaborate to make sure that critical IP blocks needed by early process adopters are on early shuttle test chips.

Integration, Verification Evolution

The shift left also creates the need for faster subsystem integration and assembly as well as the retargeting of existing subsystems, the prototyping of new ones, along with performance, power and area (PPA) analysis.

There are key changes in hardware verification too. The trend towards metrics-driven closure, and unified verification methodology (UVM) is picking up speed. Verification IP (VIP) plays a critical role in both providing proxies for incomplete aspects of the system, as well as a vital role in proving adherence to interface standards.

Simulation remains the main workhorse for IP and subsystem verification, and emulation has taken center stage for SoC hardware verification, HW/SW integration and OS bring-up. Specialized hardware for emulation, acceleration and prototyping is being applied by a much broader set of design teams to accelerate regressions and open the door to software-driven hardware verification methodologies.

Advanced Nodes

While 28nm is humming along at record adoption levels, 20nm products are rolling, and the first 16nm/14nm chips are getting ready to hit the fabs. At the same time, 10nm enablement is already quite far along, and close on its heels is 7nm.

What have made these rapid advances possible have been a vertical collaboration structure with industry leaders and the most rigorous process of co-optimization across the collaboration elements yet. “Vertical co-optimization” essentially turns a process that was a series of steps into a parallel process.

While the serial process (Figure 1) was easy to manage because each step was self-contained, it yielded sub-optimal results. Also, if it is ultimately determined that the value of a node is not being realized, it is a big schedule setback to have to restart a serial process.

Figure 1: Previous serial enablement process

In contrast, the vertical co-optimization approach (Figure 2) offers many opportunities to see how decisions in one realm affect the other elements of the enablement ecosystem. This change enables mutual trade-offs for optimization versus the old model of optimizing one step, holding it fixed, and passing the outcome onto the next step.

Figure 2: New vertical co-optimization process

Take, for example, design rule checks (DRCs). At a basic level, DRCs define what a router (and placer) can legally do when physically implementing a design. The rules can be expressed in different ways. Standard cells can be constructed in different ways, with more or less placement interaction, to be more compact, or with more flexible pin access.

Rules can also be implemented into routers in different ways, with full precision, or with simpler modeling but more conservative precision. IP implementers can choose 12-track or 7.5-track libraries, with more or fewer metal layers. All of these decisions combine in complex ways to yield a tool runtime profile, a design or IP density profile, an achievable timing performance, and even a time to market benefit.

Packaging/PCB

Form factors, price points, performance and power are driving a boom in innovation in the packaging. The lines between PCB, package, interposer and chip are being blurred.  For example, the fan out wafer level package (FOWLP) is rapidly becoming the solution of choice in the mobile industry for its ability to handle a large number of pins at a low cost and in a very small form factor.

The foundry encroachment into the Outsourced Assembly and Test (OSAT) space began with silicon-based 2.5D interposer technology, and through silicon via (TSV) 3D die stacking offerings.  As the pitches get finer on organic substrates and pricing on silicon options comes down, the foundries and the OSATs will be on an innovation spree to vie for dominance.

Figure 3: The future has a third dimension

Having design environments that are familiar to the principle in the system interconnect creation–regardless of being PCB, package or die centric by nature–provides a cockpit from which the cross fabric structures can be created, and optimized.  Being able to provide all of the environments also means that interoperable data sharing is smooth between the domains.  Possessing analysis tools that operate independent of the design environment offers the consistent results for all parties incorporating the cross fabric interface data.

For example design IP offerings for PCIE4, HBMII, LPDDR4 and the like let the specialists encapsulate the complexity of implementation of these standards in FinFET technology and deliver not only the IP itself, but also critical models/analysis capabilities that offer contextual use case assurance on top of silicon test chips.

Summary

There are two main forces that are behind these trends: The ceaseless march of technology and customer demand. The products that our ecosystem has enabled over the past 30 years have kindled a demand for more and more functional systems. We’re victims of our own success, but that’s a great problem to have!

Building on this for succeeding generations of technologies requires a holistic view of system design that an EDA/IP provider can bring to the table. 2015 is filled with technical and business challenges, but we look forward to tackling them head on.

Chi-Ping Hsu is chief strategy officer for EDA products and technologies at Cadence and chief of staff to the CEO. Prior to joining Cadence in 2003, Hsu was president and chief operating officer of Get2Chip Inc. and before that held executive management positions at Avant! Corporation, where he was responsible for corporate and technology strategy, product development and marketing.