Faraday Technology Corporation announces the availability of its 4-port Gigabit Ethernet PHY on UMC’s 28HPC+ process. This silicon-proven GPHY features an SAR ADC for superior PPA advantages and an advanced digital algorithm that significantly enhances SNR (signal-to-noise ratio). Designed to meet the growing demands for highly integrated SoC solutions in networking, consumer, and industrial automation applications, Faraday’s latest offering aims to expedite product development while boosting performance.
One key feature of this 28nm 4-port Gigabit Ethernet PHY is its 33% reduction in power consumption per port compared to the previous design. Additionally, its advanced DSP (digital signal processing) mitigates signal noise from multi-port crosstalk, improving signal quality with a notable 1-2 dB SNR enhancement compared to Faraday’s 40nm 4-port GPHY. This GbE PHY supports various industry-standard protocols, including 1000BASE-T, 100BASE-TX, 10BASE-Te, 100BASE-FX, IEEE 802.3, 802.3u, 802.3ab, and ANSI X3.263-1995 (FDDI-TP-PMD). Furthermore, it seamlessly integrates with UMC’s 3.3V and 1.8V I/O, making it an ideal choice for the 28HPC+ low-power SoC platform, ensuring exceptional power efficiency and performance.
