Mixed-signal ICs are increasingly common in automotive, internet of Things (IoT), medical, industrial, consumer, and other applications. Designing mixed-signal ICs is more complex than simply designing an analog section and a digital section. There’s the interactions and interconnections between the sections, and the need to integrate software into the final solution. That makes designing mixed-signal devices especially challenging.
The varying mix of analog and digital elements further complicates the selection of the optimal design process. The analog section with a smaller amount of digital logic dominates some designs. In other cases, digital processing, memory, and I/Os are the dominant elements. That has resulted in the development of different development environments optimized for specific use cases, like an analog-on-top (AoT) methodology for analog-centric devices and digital-on-top (DoT) for digital-centric devices.
Regardless of which domain is dominant, co-simulation between the analog and digital domains can be an efficient approach. For example, Verilog and Spice can be operated in separate simulation domains and linked through what’s called inter-process communications (IPC). That can help speed up the simulation process, but it still has limitations.
Instead, the analog models can be converted into real number models (RNMs). The use of RNMs makes it possible to operate in the digital simulation environment. For top-level mixed-signal verification, converting analog models into RNM models can support the use of mixed-signal metric-driven verification (MS-MDV) that can automate debugging and pass/fail checking for all stimuli and tests.
Modern mixed signal ICs can be complex devices with multiple feedback loops through the digital and analog domains creating a multilayered fusion between the domains. The domain boundaries are not clear-cut, and the interactions are complex. That requires a tightly integrated mixed-signal verification environment like the Virtuoso AMS Designer Simulator from Cadence that integrates MATLAB and Simulink into the hardware design flow for mixed-signal IC development (Figure 1).
Digital control and calibration
Further increasing the complexities of mixed-signal IC design and verification is the increasing use of digital control, digital calibration, and digital signal processing. To accommodate the wide range of mixed-signal IC designs, Siemens’ Symphony Mixed-Signal Platform is based on a modular architecture that leverages the company’s Analog FastSPICE (AFS) circuit simulator to provide the fastest mixed-signal simulation performance with nanometer (nm) SPICE accuracy and capacity of 20 million SPICE elements.
Symphony works with a range of digital solvers, allowing users to maximize reuse of their existing verification infrastructure, including test benches, stimuli, scripts, post processing, encrypted IP blocks, and digital/analog netlists. Transistor level analog descriptions can be implemented using standard SPICE formats or Verilog-A HDL. The digital blocks can be described in Verilog, SystemVerilog, VHDL, or encrypted IP. The configurable architecture also integrates into schematic capture flows and supports both analog- and digital-centric methodologies (Figure 2).
Shrinking nodes bring growing challenges
Power consumption is an important factor in defining the quality of mixed-signal IP and needs to be considered early in the design. Managing power is getting more challenging as processes continue to scale smaller. Moving to the 28-nm process node can be especially challenging with regard to power consumption in mixed-signal designs.
Before the challenges experienced at 28 nm, standard voltage threshold (standard Vth) devices were suitable to enable IP to be ported between processes and foundries. The need for reduced supply voltage and leakage current reduction, plus other factors at 28 nm, can make it impractical to use standard Vth devices.
For example, Figure 3 shows the sample ring-oscillator frequency vs. technology node for 65-, 40- and 28-nm processes from two foundries. The corner spread due to global device variation is much wider in 28-nm. This corner spread makes it more challenging to meet circuit specifications across all corners. To prevent this increased variation in circuit performance due to process and corner spread, design tools like Synopsys’ DesignWare Mixed-Signal PHY IP portfolio can be used to control specific factors more tightly in the design, such as power supplies through regulation or stringent specification requirements.
Designing mixed-signal ICs is complex, and it’s getting more difficult. The use of AoT or DoT methodologies is giving way to co-simulation approaches. For top-level mixed-signal verification, converting analog models into RNM models can support more efficient development processes. Configurable and flexible environments can be important to speed the development of complex mixed-signal ICs, especially at the 28-nm process node.
Analog Mixed-Signal design and simulation flow, Siemens
Mixed-Signal IP Design Challenges in 28-nm Process and Beyond, Synopsys
Solutions for Mixed-Signal SoC Verification Using Real Number Models, Cadence