Power ICs cover a variety of functions, from high voltage application-specific ICs (HV-ASICs) to power management ICs (PMICs). Each type of power IC has unique design challenges and needs specific design tools.

This FAQ reviews some of the challenges related to HV-ASICs for applications like gate drivers for power semiconductor devices, pin drivers for automatic test equipment (ATE), and drivers for microelectromechanical system (MEMS) devices, and PMICs for monitoring, sequencing, regulating, optimizing and other power-related functions, and presents some tools for PMIC design.

HV-ASICs that combine digital, analog, and high-voltage technologies can be especially challenging and require specialized tools and an understanding of parasitics, high-voltage electric fields, thermal management, and layouts that support specific isolation needs.

Designs need to consider degradation mechanisms like time-dependent gate oxide breakdown, also called time-dependent dielectric breakdown (TDDB) in power semiconductor devices, negative bias temperature instability (NBTI) that’s an increase in the threshold voltage causing degradation of the mobility, drain current, and trans-conductance in MOSFETs, hot carrier degradation (HCI) that can degrade gate oxides, and electromigration that can result in short or open circuit connections.

Among the subtle but critical design factors are parasitic extraction and layout strategies:

• Under high-voltage operation, parasitic capacitors can inject charge into high-impedance nodes, leading to crosstalk with sensitive analog circuitry, local overvoltage conditions, or device breakdown. Inadequate layout can be a contributor to parasitic fields.
• The layout needs to consider the creepage and clearance distances needed in the HV-ASIC as well as the package design. It should also consider the dielectric thickness needed to support specific operating voltages. Improper layout can lead to parasitic device turn-on or undesired leakage currents. High-frequency applications like driving gallium-nitride (GaN) or silicon-carbide (SiC) power transistors can be especially challenging to lay out (Figure 1).

PMIC design challenges
PMICs don’t use HV technology. They manage, monitor, convert, and regulate lower voltages and power to maximize battery life, optimize system efficiency, and reduce power consumption in devices ranging from wearables to servers and automobiles. There are several performance areas to optimize when designing PMICs including:

Efficiency and power loss are critical performance metrics and can be challenging to optimize. Design considerations include balancing switching and conduction losses in power semiconductors, minimizing the resistance and parasitics in inductors and capacitors, and power consumption of the device in low-power and standby modes.

Thermal management for PMICs is challenging and must consider heat generated by the device as well as the thermal environment in which the device operates. The PMIC generates heat because of voltage regulation and conversion, especially in high-current devices. PMICs are often used in very tight PCB layouts that can limit opportunities for cooling the device and can couple heat from surrounding loads like large digital ICs into the PMIC.

Power integrity and noise problems can arise from a plethora of sources and reduce the stability of the voltage regulation or cause general instability in the operation of the device. Among the challenges are fast and wide dynamic changes in the current demanded by loads that can cause significant output voltage droops and noise. The high frequency of the power devices can couple noise into power and signal interconnects. Parasitic elements from an adequate IC layout can aggravate that coupling. High-frequency switching can also produce electromagnetic interference (EMI) that can be coupled to nearby ICs.

PMIC designers can turn to tools like Allegro X from Cadence that support analysis of power distribution, voltage fluctuation, temperature distribution, heat dissipation, and other important elements of PMIC performance (Figure 2).

SPICE
SPICE (simulation program with integrated circuit emphasis) is a widely used tool for IC development and integration of ICs, including analog ICs and PMICs. Simulating an IC like a PMIC with SPICE is the standard way to verify circuit operation at the transistor level without fabricating a physical device. SPICE can be used to simulate what happens when the circuits are powered up and how they function under dynamic or fault conditions and with different voltage and current levels, temperature variations, noise, and so on. Most IC makers and suppliers of EDA tools offer proprietary variations of SPICE optimized for specific functionality.

Summary
There are different sets of design challenges for HV-ASICs and for PMICs. Specific tools are available for designing the different types of power ICs. They can simulate static and dynamic operating conditions and other aspects of device performance. In addition to proprietary design tools, there’s a range of implementations of the industry standard SPICE software optimized for specific use cases.

References
Challenges in Power Management IC (PMIC) Design, Cadence
High voltage ASICs, MinDCet
SPICE, Wikipedia